When models outpace chips, how will next‑gen AI computing systems evolve?

When Models Run Faster Than Chips, How Will the Next-Generation Intelligent Computing Systems Evolve?

From September 20 to 21, the PAIR Conference 2026 on the theme “Frontiers of Next‑Generation Physical Intelligence” was held in Shanghai. The conference, organized by the Shanghai Institute of Physical Intelligence and Robotics, invited numerous experts and scholars from universities, research institutions, and industry to discuss topics such as next‑generation intelligent computing systems, next‑generation intelligent carriers, next‑generation scientific discovery, and next‑generation computing paradigms.

In the special forum “Next‑Generation Intelligent Computing Systems: Co‑Reconstruction from Chip to Software,” the speakers discussed the technological evolution of AI computing infrastructure from perspectives of embodied intelligence, novel chip architectures, domestic computing power, and inference systems.The concluding roundtable focused on the relationship between models and chips: when large‑model iteration outpaces chip development, how can algorithms and hardware cooperate to meet continuously changing computing demands?

The round‑table discussion was chaired by junior researcher Zhu Keran from the Institute of Integrated Circuits and Micro‑Nano Electronics Innovation at Fudan University, with five guests from chip development, algorithm research, and computing systems participating in the dialogue. They are Vice President Guo Wei of Shanghai Dongfang Suanxin Technology Co., Ltd.; Assistant Professor Yu Chao of Tsinghua University Shenzhen International Graduate School; Assistant Professor Zhu Haozhe of the Institute of Frontier Technology for Chips and Systems at Fudan University; Co‑founder and Chief Scientist Cheng Zengguang of Light‑Based; and Assistant Researcher Shan Yingdi of the Department of Computer Science at Tsinghua University.

Model architectures and computational demands evolve rapidly, while chips typically take years from design to mass production. Algorithm researchers strive to improve the utilization efficiency of existing hardware, and chip manufacturers respond to new demands through architectural and software optimizations. Meanwhile, model companies are beginning to develop their own chips, and chip makers are extending into the model and software domains. When the iteration cycles of algorithms and hardware differ, how should the two sides adapt? As industry boundaries become increasingly blurred, who will define the next‑generation intelligent computing system?

Image | (left to right) Zhu Keren, Cheng Zenguang, Guo Wei, Shan Yingdi, Yu Chao, and Zhu Haozhe hold a roundtable discussion (source: PAIR)

Around these questions, the guests combined their own research and industry practice to offer differing assessments of the technology roadmap and industry landscape.

The following content is compiled from the roundtable discussion.

Model iteration is too fast, chip development is too slow

Guo Wei noted that it typically takes three years for a generation of chips to go from architecture design to mass production, while the computational methods and application demands of large models may change multiple times during that period. Facing different iteration paces, is it the algorithm that dictates the hardware, or the hardware that dictates the algorithm?

Guo Wei believes that in the short term, model deployment is still limited by the computing power, storage, bandwidth, and interconnect conditions of existing chips; even if a model performs well in papers, practical deployment efficiency must be considered.“The models that are truly deployed today are not necessarily the most compute‑optimal, but they are certainly the best matched in software and hardware.” In the long run, chip design will be driven by algorithmic demands, creating a mutually iterative relationship.

Shan Yingdi explains this relationship through the history of algorithm development. He uses the evolution of recurrent neural networks (RNN), long short‑term memory networks (LSTM), and Transformers as examples, pointing out that whether a model can fully exploit existing computational resources is itself a key factor influencing its development.

Compared with traditional recurrent neural networks, Transformers are easier to implement parallel computation and can make more efficient use of large-scale computing resources. This means that whether a model becomes mainstream depends not only on its algorithmic performance but also on whether it can adapt to the computational characteristics of existing hardware. On the other hand, hardware is continuously being adjusted to meet the computational demands of algorithms.

Shan Yingdi noted that dedicated compute units in GPUs such as Tensor Cores, as well as support for low‑precision computation, are designed to enable hardware to execute model operations more efficiently. This also shows that the adaptation between algorithms and hardware is not one‑way but a mutually reinforcing process. Therefore, Shan Yingdi believes that in the short term algorithms need to align more closely with hardware, because algorithmic iteration is far faster than hardware development; but in the long run, the two will gradually evolve synergistically.

Yu Chao emphasizes the leading role of algorithms. She points out that researchers often first adjust implementation methods on existing hardware and explore new intelligent architectures, after which hardware development optimizes for algorithmic needs. “In my view, algorithms still take the lead because algorithm researchers can propose new implementation ideas more quickly,” Yu says.

However, the algorithm-first approach does not mean it can exceed hardware limitations. Zhu Haozhe uses embodied intelligence as an example to note that when deploying robot models, one often has to choose a hardware platform that can meet real‑time requirements, such as Jetson Orin (NVIDIA’s embedded computing platform for robotics, autonomous driving devices, and edge AI applications). Constrained by chip compute capacity and power consumption, the scale of models and computational operators researchers can use are limited. Yet Zhu also believes that, over a longer historical span, once a class of algorithms achieves a clear advantage on a specific task, hardware will eventually converge toward it.

Although the guests have different focuses, they all point out that models and chips cannot evolve independently: short‑term algorithms are constrained by existing hardware, and long‑term hardware must respond to algorithmic demands.So, how should the current chip ecosystem address rapidly changing compute requirements?

When chips can’t keep up with models, who will change?

As algorithms iterate, models place new demands on compute performance, bandwidth, and energy efficiency. Faced with this shift, should the chip industry continue optimizing mainstream CMOS (complementary metal‑oxide‑semiconductor) technology, or seek breakthroughs through new materials and architectures?

Cheng Zengguang believes that the value of new computing technologies lies precisely in addressing the high bandwidth and low power consumption challenges that traditional silicon‑based chips struggle to balance.Take optical computing as an example: when the conventional Von Neumann architecture faces storage bandwidth and power‑consumption bottlenecks, using light for part of the computation may offer a new solution. However, Cheng does not think that new materials or architectures necessarily mean abandoning silicon technology altogether.

Guo Wei shares a similar view. He points out that CMOS has built up a mature process ecosystem over the past few decades, still offering clear advantages in cost, yield, and engineering implementation. While optical computing shows potential in certain matrix‑operation and interconnect scenarios, relying entirely on optical computing for large‑scale model inference remains challenging at present.Therefore, he judges that technologies such as optical computing and new materials are more likely to first appear as co‑processors, and then, through 2.5D packaging or three‑dimensional integration, work synergistically with traditional compute chips.“At this stage, it’s not a replacement, but an incremental addition,” Guo said.

Zhu Haozhe further pointed out that when evaluating the performance advantages of new computing technologies, one should not only look at the performance of individual devices or compute arrays, but also consider the actual system-level benefits. He noted that some research papers on emerging computing technologies report performance improvements of several orders of magnitude, but in a complete system these advantages may be offset by additional data processing and conversion overhead.

For example, optical computing must account for the time and energy of optoelectronic conversion and data orchestration; in‑memory computing must consider the cost of peripheral circuits, ADC/DAC conversion, and data reshuffling. Therefore, he believes that emerging computing technologies are more likely to achieve breakthroughs in specific parts of existing systems, such as storage or interconnect, rather than replacing the entire CMOS‑based computing stack in one go.

From this perspective, changes in the chip ecosystem are more likely to manifest as the collaboration of different technologies rather than simple substitution. At the same time, the original upstream‑downstream division in the computing power industry is also shifting.

On one hand, model or internet companies such as OpenAI, Google, and ByteDance are exploring custom chips; on the other hand, chip manufacturers are beginning to study models to better understand algorithmic requirements.

Cheng Zengguang believes that general‑purpose graphics processing units (GPUs) need to handle multiple computing tasks, some of which are not essential for specific models. If model companies develop application‑specific integrated circuits (ASICs), they could reduce redundancy and improve computational efficiency.

Guo Wei explained this trend from both cost and technical demand perspectives. First, training and inference of large models require a continuous investment of massive computing power, so model vendors naturally want to reduce chip procurement and usage costs. Second, the hardware iteration of general‑purpose GPUs may not be able to keep up with the constantly changing requirements of specific models, making self‑developed chips a viable option.

At the same time, traditional chip manufacturers are also extending into the algorithm and software domains. Guo Wei noted that Nvidia has a dedicated team for AI model research, and Dongfang Suanxin is also conducting related studies. However, they research foundational models not to compete directly with model companies, but to use the models to validate hardware, optimize hardware‑software integration, and provide more complete system solutions. “If a pure chip or hardware company only sells hardware, only sells chips, it will gradually become marginalized,” Guo Wei said.

But having algorithmic capabilities does not mean model vendors can easily overcome the technical barriers of the chip industry. Zhu Haozhe uses the collaboration between OpenAI and Broadcom as an example to point out that developing large‑scale compute chips involves far more than defining a single computing architecture; it also includes packaging, interconnects, supernode design, networking, and other complex system‑engineering challenges.

Yu Chao also emphasizes that even if model companies have a clearer understanding of their compute needs, once they enter the chip industry they still face the same challenges common to the traditional semiconductor sector, such as manufacturing processes and advanced packaging. In her view, the real uncertainty remains the timeline. When there is a generational gap of several months or even longer between model vendors and traditional chip manufacturers, it is still difficult to determine which side will gain the advantage.

Zhu Haozhe believes that model vendors will find it difficult to independently complete the entire chip process from design to deployment in the short term, but they are increasingly participating in architecture design, influencing the product definition rights of traditional chip companies.

Model vendors are extending into hardware, and chip vendors are extending into software and models, all to make compute supply better match algorithmic demand. This bidirectional infiltration may also reshape industry division of labor and the definition of chip architectures.

Next‑generation compute, ultimatelywho will define it?

Beyond the mutual adaptation of models and chips, the expansion of AI application scenarios is also reshaping compute demand. From data centers to embodied intelligence, autonomous driving, and other edge devices, each scenario has different requirements for performance, latency, power consumption, and cost.

As AI moves from dialogue to complex agents, inference tasks become increasingly diverse: Will the main growth in the future come from large data centers or from endpoints such as robots? Will the models that support these applications be dominated by open source or proprietary solutions?

Cheng Zengguang believes that in the short term, servers and AI compute centers remain the more mature scenarios for inference deployment. However, in the long run, edge devices such as robots, autonomous driving systems, and home local computing will generate increasingly more demand. These scenarios differ markedly from data centers. Robots need to react to the environment in real time, autonomous driving systems have strict latency and reliability requirements, and home devices also need to consider privacy protection and power consumption. Different tasks have varying computational requirements.

Guo Wei also believes that large AI compute clusters remain essential infrastructure for running massive foundational models and complex agents, but private deployment and edge applications also have growth potential. With the development of models such as DeepSeek and Kimi, enterprises can deploy models locally that meet their own business needs while also safeguarding data privacy and information security. In embodied intelligence scenarios, the edge can handle data collection and some front‑end processing tasks, collaborating with the cloud.

Shan Yingdi explained this divergence by the changes in model capabilities. On one hand, model sizes continue to grow, and agents can perform increasingly complex tasks. For long-running tasks that require substantial computing resources, cloud data centers still have an advantage. On the other hand, models with relatively smaller parameter counts are constantly improving and can now accomplish tasks that were previously difficult. In scenarios such as autonomous driving, embodied intelligence, and those with high privacy requirements, some tasks must be completed by edge-side computing. Therefore, he believes that the demand for computing power on both cloud and edge will continue to grow.

Zhu Haozhe cautioned that different dimensions of market growth need to be distinguished. If measured by high‑value subscriptions and compute‑service revenue, the cloud may still hold the advantage; if the focus is on user numbers, application scenarios, and new business models, the edge could offer greater expansion potential. Moreover, the two are not necessarily mutually exclusive. For example, the development of embodied intelligence will increase computing demand on robot edges, but it may also drive growth in cloud computing power.

Yu Chao believes that whether computation occurs in the cloud or on the edge, the total amount of societal computing resources is increasing, and the key is how to fully leverage these resources through software.

Another line of discussion running parallel to deployment models is the openness versus closedness of models.

Cheng Zengguang, from the perspective of hardware manufacturers, hopes the software ecosystem becomes more open, reducing software barriers in hardware applications.

Guo Wei believes that open‑source and closed‑source models will coexist for the long term. He points out that Chinese model companies, operating under relatively limited compute resources, have developed a distinctive open‑source development path. As model capabilities continue to improve, the performance gap between open‑source and closed‑source models is narrowing. However, he still leans toward the view that closed‑source models will play a larger role in breakthrough frontier capabilities, while open‑source models are expected to become more widely adopted in various practical applications.

Shan Yingdi believes that closed‑source models can more easily form a commercial loop through service revenue, reinvesting the profits into compute and model R&D, thus potentially maintaining a frontier‑capability advantage in the short term.

But he also notes that open‑source models are attractive in terms of transparency and privacy, and their usage may continue to expand. He likens the two to Apple and Android: the closed‑source ecosystem may capture more profit, while the open‑source ecosystem could reach a larger user base.

Yu Chao’s perspective comes mainly from practical experience in open‑source software development. She mentioned that the team once explored turning open‑source software into commercial revenue, but found that relying directly on open‑source for profit is not easy. In contrast, open‑source software can serve a broader developer community, promote technology adoption, and by forming a software ecosystem, indirectly drive the application and sales of related hardware products. Therefore, she places greater emphasis on the long‑term value of open‑source software for building a technological ecosystem.

Zhu Haozhe offers a different view on “open‑source” in the era of large models. Traditional software open‑source usually means developers can obtain the source code, run it in their own environment, modify it, and reproduce it. But for models whose parameter count reaches the trillion‑scale, even if the model weights and code are released, actually running them still requires massive computational resources that ordinary SMEs or universities cannot easily afford. Therefore, Zhu believes that open‑sourcing large‑scale models is already different from traditional software open‑source. While releasing model weights and code can increase transparency and build social trust, it does not necessarily mean external researchers can fully reproduce the model’s operation and research process.

He also believes that the improvement of AI code‑generation capabilities could change the traditional open‑source collaboration model that relies on individual developer contributions.

From cloud‑edge collaboration to the coexistence of open‑source and closed‑source, these discussions show that future compute architectures must not only accommodate diverse task demands but also be shaped by model ecosystems and business models.

This leads to the final question of the roundtable: among chips, models, infrastructure, and applications, who will capture the most commercial value?

Cheng Zengguang believes that currently hardware vendors such as Nvidia hold strong pricing power in overseas markets, but as the inference market expands, model, cloud service, and application companies may also gain more opportunities.

Guo Wei’s assessment differs. He believes that in the long run, application endpoints that truly understand user needs still have a chance to hold pricing power. At the same time, chips, foundational models, and compute services will earn different profit margins based on the value they create, and dominance will not necessarily remain with a single company.

Shan Yingdi is more optimistic about both hardware and model sides. In his view, chip companies currently have strong profitability, largely because compute supply is relatively insufficient. Whether chips can continue to maintain high margins in the future will depend on the relationship between the growth rate of model compute demand and the speed of chip capacity expansion. At the model layer, as AI capabilities improve, users may be willing to pay higher fees for more complex and valuable tasks.

In contrast, training and inference infrastructure software in the middle layer may not achieve similarly high profits due to the proliferation of open‑source technologies. Yu Chao also leans toward being bullish on chip and foundational model companies. He describes chip manufacturers as “shovel sellers”: regardless of what models and applications emerge in the future, they will all need underlying compute support.

Zhu Haozhe starts from the phenomenon of AI lowering the barrier to software development and raises another thought‑provoking question. In the past, building an application required a large amount of engineering resources, but as code‑generation capabilities improve, the development cost of some applications is decreasing. When application development becomes easier, the technical barriers of ordinary software products may also drop. In this situation, companies that provide underlying compute power and foundational models may actually retain a strong commercial advantage.

The guests did not reach a consensus on profit attribution, but they all highlighted the shifting dynamics of the industry: model demand influences hardware definition, chip performance limits algorithm deployment, and application scenarios drive adjustments in models and computing systems. Model companies are entering chip design, chip companies are extending into software, models, and system solutions, and the original boundaries are gradually blurring.

The challenge of next‑generation intelligent computing systems is not only to boost the performance of a single chip, but also to enable computing technologies at different levels to adapt to rapidly changing algorithms and application demands.How this collaboration will shape industry division of labor, and who will ultimately hold the definition and pricing power, remains unanswered.

Operations/Typesetting: He Chenlong

Note: Cover/lead image generated with AI assistance